The present invention relates to datapath processing. In one embodiment, the present invention relates to apparatus and methods for high-performance, datapath processing. The present invention is particularly useful for programmable logic devices (PLDs).
Many modern processing applications (e.g., packet processing, digital signal processing, digital image processing) require both high-performance and high flexibility. Existing processing devices, however, typically provide inflexible pipeline architectures that have several shortcomings. For example, pipelined processing devices are limited in their speed. To guarantee that each stage executes properly, a pipelined device can only operate as fast as the slowest stage of the pipeline. Moreover, such pipelines typically operate in a sequential manner, whereby each unit of data must pass through each stage of the pipeline regardless of processing variables (e.g., the type of data or the mode of operation). Such inflexibility can cause inefficiencies and delays. It would therefore be desirable to provide a high-performance and flexible data processing apparatus.